Many ICs are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. It is generally desirable that ICs operate as fast as possible, and consume as little power as possible. Semiconductor ICs often include one or more types of memory, such as CMOS memory, antifuse memory, and E-fuse memory.
One-time-programmable (“OTP”) memory elements are used in ICs to provide non-volatile memory (“NVM”). Data in NVM are not lost when the IC is turned off. NVM allows an IC manufacturer to store lot number and security data on the IC, for example, and is useful in many other applications. One type of NVM is commonly called an E-fuse.
E-fuses are usually integrated into semiconductor ICs by using a narrow stripe (commonly also called a “fuse link”) of conducting material (metal, polysilicon, etc.) between two pads, generally referred to as anode and cathode. Applying a programming current (Iprog) to the E-fuse destroys (fuses) the link, thus changing the resistance of the E-fuse. This is commonly referred to as “programming” the E-fuse. The fuse state (i.e., whether it has been programmed) can be read using a sense circuit, which is common in the art of electronic memories.
During programming, current is applied through the fuse link for a specified period. The programming current heats up the fuse link more than the adjacent areas due to current crowding and differences in heat dissipation, creating a temperature gradient. The temperature gradient and the carrier flux causes electro- and stress-migration to take place and drive material (e.g., silicide, dopant, and polysilicon) away from the fuse link.
Programming generally converts the E-fuse from an original resistance (e.g., about 200 Ohms) to a programmed resistance (e.g., greater than 10,000 Ohms). It is desirable for the programmed resistance to be much higher (typically many orders of magnitude higher) than the original resistance to allow reliable reading of the E-fuse using a sensing circuit. A first logic state (e.g., a logical “0”) is typically assigned to an unprogrammed, low-resistance fuse state, and a second logic state (e.g., a logical “1”) to the programmed, high-resistance fuse state. The change in resistance is sensed (read) by a sensing circuit to produce a data bit.
FIG. 1A is a diagram of a prior art E-fuse cell 100. The E-fuse cell 100 includes an E-fuse 102 with an E-fuse link 104. The E-fuse link 104 is often polysilicon, silicided polysilicon, or other suitable fuse link material. The E-fuse cell 100 is incorporated into an IC having multiple gate oxide thicknesses. Transistors M1, M2, M4 and M5 have been fabricated using a thicker oxide, which allows relatively higher voltages to be applied to these transistors. PMOS transistor M3 and transistors (not separately shown) in the sense and latch block 106 have been fabricated using a thinner oxide, which allows these transistors to operate at a lower voltage, which can be a core voltage as low as about one Volt. Fuse voltage (“Vfs”) is a voltage supply pad typically shared by many fuses in an E-fuse memory array and is used to program the E-fuse 102, as described in association with FIG. 1B.
FIG. 1B is a diagram of the E-fuse cell of FIG. 1A illustrating a programming operation. During a programming operation, PROGRAM enable (“En_pgm”) is a logic one (HIGH), READ enable (“En_read”) is a logic zero (LOW), and a programming voltage (typically about 2.5 V to about 3.3 V) is applied to Vfs. Transistors M2 and M4/M5 are OFF and M1 is ON. Programming current, represented as line 108, flows from Vfs through the fuse link 104 and transistor M1 to ground. This current is typically about 10 mA for a selected period (programming time, Tpgm) and changes the resistance of the fuse from a low-resistance condition to a high resistance condition, as described above. Transistor M2 isolates, and thus protects, the thin-oxide transistors (e.g., M3) from high voltage on the programming path 108. Transistor M1 has a relatively large gate width in order to sink the programming current, and thus occupies a large percentage of the E-fuse cell area.
FIG. 1C is a diagram of the E-fuse cell of FIG. 1A illustrating a READ operation. During a READ operation, En_read is a logic 1 and En_pgm is a logic zero. No voltage is applied at Vfs. Transistor M1 is OFF, and transistors M2, M4, and M5 are ON. Transistor M3 is also ON because the gate of M3 is grounded. Transistors M3, M2, the fuse 102, M4, and M5 form a voltage divider with an output at node A. Transistors M4, M5, and M2 are designed to be strong (thick oxide devices) and to have sufficiently low resistances when ON so that they do not have an appreciable effect on the voltage at node A. The voltage at node A is primarily a function of M3 and the fuse resistance. Although the fuse link is typically “blown” in a programming operation, the result is a high-resistance path through the fuse 102, thus the fuse link is represented as providing an electrical path, whether representing a pristine (as-fabricated) or programmed (blown) condition.
When the fuse is unprogrammed (low resistance), node A is at a relatively low voltage during a READ operation. When the fuse has been programmed (high resistance), node A is at a high voltage during a READ operation. During a READ operation, the sense and latch block 106 senses the voltage at node A and produces a first logic value for a programmed fuse and a second logic value for an unprogrammed fuse.
Since transistor M4 is directly connected to a pad, it needs to follow special layout rules for ESD and latchup protection. These layout rules typically include guard rings and stacking the M4 transistor on top of another NMOS transistor (i.e., M5), which uses significant area on the silicon IC.
E-fuse memory arrays that provide more efficient use of silicon area are desirable.